1. Field of the Invention
The present invention relates to a semiconductor memory device including sense amplifiers.
2. Description of the Related Art
As a representative example of a semiconductor device including sense amplifiers, dynamic semiconductor memory devices are known. A sense amplifier is used to amplify a minute differential voltage corresponding to data stored in a memory cell from among the memory cells, and read the data, the differential voltage being output from paired bit lines connected to memory cells.
The semiconductor memory devices of recent years each have an enhanced integration density and an increased memory capacity, while further power consumption reduction and high speed operation are demanded. In order to reduce power consumption in a semiconductor memory device, it is effective to decrease the operating voltage of the inner circuit of the semiconductor memory device. For example, where an external power supply voltage of +1.8 V is supplied to a semiconductor memory device, an internal power supply voltage of +1.1 V may be generated by a step-down circuit to supply the internal power supply voltage to a memory cell array (including a plurality of memory cells, and, e.g., decoders for accessing the memory cells and sense amplifiers). An internal power supply voltage is a charge voltage corresponding to data “1” stored in a memory cell, and is also a high potential-side power supply voltage for a sense amplifier.
When an internal power supply voltage is decreased to decrease the charge voltage for bit lines, the operating voltage of a sense amplifier is also decreased in a known bit line ½ equalization method, resulting in an increase in sensing time. Sensing time is time required from the start of a sense amplifier to a point where a differential voltage (voltage difference) reaches a predetermined value at which the differential voltage can be regarded as being constant, after the differential voltage is output from a memory cell onto paired bit lines and amplified. Such a predetermined differential voltage is reached when, for example, a voltage on a high-side bit line reaches a value of 95% of an internal power supply voltage.
When reading data from a semiconductor memory device, in general, first, a word line is activated, and subsequently, memory cells are selected. A differential voltage corresponding to retained data is output onto respective paired bit lines from each of the memory cells. Then, sense amplifiers are started, and at the point of time when output values of the sense amplifiers are determined, data output from a sense amplifier from among the sensor amplifiers is selected by a column selection signal decoded by a column decoder and output to the outside. In other words, in order to properly read data from a memory cell, it is also necessary to set a time when a word line is selected to the time when data is selected by a column selection signal and is output, depending on the sensing time. This means that the longer the sensing time, the slower is the speed of reading data from the semiconductor memory device is.
As a method for solving such problem, for example, Japanese Patent Application Laid-open No. 2008-186547 discloses a method for reducing sensing time by providing shared MOS transistors that operate as switches between a sense amplifier and bit lines to shut off the bit lines and thereby reduce the load (capabilities of the bit lines) on the sense amplifier during amplification of a differential voltage by the sense amplifier. However, when the sense amplifier and a bit line are disconnected by a shared MOS transistor, the effect of noise resulting from a coupling capacity between a bit-line wiring between the shared MOS transistor and the sense amplifier (hereinafter referred to “in-sense-amplifier bit line”) and a wiring adjacent to the in-sense-amplifier bit line (for example, another in-sense-amplifier bit line) is increased, which may result in inversion of amplified data or the occurrence of erroneous sensing. In particular, when an internal power supply voltage is decreased, differential voltages output from the respective paired bit lines to the sense amplifiers are also decreased, and thus, the possibility of erroneous sensing is increased. Japanese Patent Application Laid-open No. 2008-186547 discloses a technique for decreasing voltage applied to the gate of a shared MOS transistor SHR in two steps when a sense amplifier and a bit line are disconnected, in order to prevent such erroneous sensing.
In the aforementioned technique disclosed in Japanese Patent Application Laid-open No. 2008-186547, voltage applied to the gate of a shared MOS transistor is decreased in two steps, requiring a control circuit and a control wire for such two-step decrease. Accordingly, the size of the control circuit included in the semiconductor memory device is increased, and the addition of control wires, which may cause noise, increases the risk of causing the semiconductor memory device to malfunction.
For the semiconductor memory devices of recent years, a further density increase has been studied and their wiring widths and wiring pitches tend to be increasingly smaller in order to increase their memory capacities. Accordingly, it is desirable not to increase the size of the control circuit and the number of control wires to the greatest possible extent.